In conventional nonvolatile semiconductor memory devices, elements have been integrated in a two-dimensional plane on a silicon substrate. Although the dimensions of one element have been reduced in order to increase the memory capacity of memory, such downscaling is becoming difficult these days in terms of cost and technology.
In contrast, collectively processed three-dimensionally stacked memory is presented. The collectively processed three-dimensionally stacked memory includes a stacked structure body including alternately stacked insulating films and electrode films, silicon pillars piercing the stacked structure body, and charge storage layers (memory layers) between the silicon pillars and the electrode films. Thereby, a memory cell is provided at the intersection of the silicon pillar and each electrode film. Further, also a configuration is presented using a memory string having a U-shaped configuration in which two silicon pillars are connected on the substrate side.
The collectively processed three-dimensionally stacked memory like this leaves room for improvement to expand the allowable margin of mask alignment accuracy and dimensional accuracy to increase productivity.